1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a super junction structure.
2. Description of the Prior Art
In a metal oxide semiconductor (MOS) device, on-resistance (Rdson) between drain and source of the device is positive proportional to power consumption of the device, and thus the power consumption of the MOS device can be reduced by decreasing the on-resistance. Furthermore, resistance generated from an epitaxial layer used for bearing voltage occupies the largest percentage of the on-resistance. Although the resistance of the epitaxial layer can be raised by increasing the doping concentration of the dopant, the epitaxial layer is used to tolerate high voltage, and the breakdown voltage of the epitaxial layer is reduced when the doping concentration is increased, so that ability to tolerate the voltage of MOS device is reduced. For this reason, a semiconductor device having a super junction structure is developed to have both high voltage bearing ability and low on-resistance.
Refer to FIG. 1, which is a schematic diagram illustrating a cross-sectional view of a semiconductor device having a super junction structure according to the prior art. As shown in FIG. 1, the semiconductor device 10 includes an N-type substrate 12, an N-type epitaxial layer 14, a plurality of P-type semiconductor layers 16, a plurality of P-type doped body regions 18, a plurality of gate structures 20, a source metal layer 22 and a drain metal layer 24. The N-type epitaxial layer 14 has a plurality of deep trenches 26, and each P-type semiconductor layer 16 respectively is filled into each deep trench 26, so that the N-type epitaxial layer 14 and each P-type semiconductor layer 16 are disposed alternatively in sequence along a horizontal direction. In addition, each P-type doped body region 18 is disposed on each P-type semiconductor layer 16, and each gate structure 20 is respectively disposed on the N-type epitaxial layer 14 between the adjacent P-type doped body regions 18. The source metal layer 22 covers the N-type substrate 12 and is electrically connected to the P-type semiconductor layer 16. Because the N-type epitaxial layer 14 and each P-type semiconductor layer 16 constitute a PN structure, i.e. the super junction structure 28, a depletion region formed between the N-type epitaxial layer 14 and each P-type doped body region 18 can be extended to be between the N-type epitaxial layer 14 and each P-type semiconductor layer 16. Accordingly, the range of the depletion region can be increased, and the vertical electric field between the N-type epitaxial layer 14 and each P-type doped body region 18 so as to raise the voltage bearing ability. Furthermore, due to the decrease of the vertical electric field between the N-type epitaxial layer 14 and each P-type doped body region 18, the doping concentration of the N-type epitaxial layer 14 can be raised to reduce the resistance of the N-type epitaxial layer 14 in a vertical direction.
Refer to FIG. 2, which is a schematic diagram illustrating a top view of the semiconductor device according to the prior art. As shown in FIG. 2, the semiconductor device 10 of the prior art has an active device region 30 and a peripheral region 32 surrounding the active device region 30. The super junction structure 28 of the prior art extends to the peripheral region 32, and each P-type semiconductor layer 16 and the N-type epitaxial layer 14 in the peripheral region 32 surround the active device region 30. In the active device region 30, a top-view pattern of each P-type semiconductor layer 16 is rectangular, and corners of the P-type semiconductor layer 16 that is most adjacent to the peripheral region 32 is a right angle. In the P-type semiconductor layer 16 most adjacent to the peripheral region 32, a distance between a first point 34 and the P-type semiconductor layer 16 in the peripheral region 32 is different from a distance between a second point and the P-type semiconductor layer 16 in the peripheral region 32, so that an uneven electric field is generated between the P-type semiconductor layer 16 most adjacent to the peripheral region 32 and the N-type epitaxial layer 14 that are in contact with each other. For this reason, the breakdown voltage that the super junction structure 28 between the active device region 30 and the peripheral region 32 can tolerated is smaller than the breakdown voltage that the super junction structure 28 in the active device region 30 can tolerated, and the voltage bearing ability of the semiconductor device 10 is limited by the super junction structure 28 between the active device region 30 and the peripheral region 32. Therefore, the voltage bearing ability of the semiconductor device 10 cannot be determined by transistor devices in the active device region 30. In addition, because the super junction structure 28 between the active device region 30 and the peripheral region 32 having right angle, electric charges are easily accumulated at corners of the super junction structure 28, and generate high electric field. Therefore, voltage breakdown of the semiconductor device 10 is easily generated.
For these reasons, to solve the problems of the voltage bearing ability of the semiconductor device limited by the super junction structure between the active device region and the peripheral region and the high electric field generated by the right angle of the super junction structure is an important objective.